1. Field of the Invention
The present invention relates to a semiconductor device capacitor, and more particularly to a semiconductor device capacitor fabrication method for obtaining a high dielectric constant in a large scale integration (LSI) semiconductor memory device by applying new materials to a dielectric thin film and an electrode.
2. Description of the Prior Art
With reference to a conventional semiconductor device capacitor, as shown in FIG. 1, there is provided a substrate 1 having a plurality of impurity diffusion regions 2 therein. An oxide film 3 is formed on the substrate 1 and then etched by a lithographic technique to pattern a plurality of contact holes therethrough. A polysilicon layer 8 is formed in the contact holes and on the oxide film 3 and then patterned. A dielectric thin film 9 is formed on the patterned dielectric thin fill 9 conductive layer 10 serving as an upper electrode of the capacitor is formed on the dielectric film 9.
As semiconductor memory devices become increasingly integrated, the size of memory cells gradually decreases and the area occupied by a capacitor in a semiconductor device decreases accordingly. Thus, the dielectric constant .di-elect cons..sub.r of the dielectric thin film 9 must be increased.
In general, the most compatible dielectric thin film applied to a known semiconductor device fabrication method is SiO.sub.2, which unfortunately exhibits a dielectric constant as low as approximately 3.8 .di-elect cons..sub.r. Also, because of limitations in thinning a dielectric film formed of SiO.sub.2, the dielectric film must be combined with other films for thereby forming a multi-fold film such as one formed of ONO (Oxide-Nitride-Oxide) or NO (Nitride-Oxide) . However, the NO thin film currently employed in the fields concerned is limited to about 4 nm even after nitridation annealing. Also, the ONO structure is not appropriate for use in an LSI semiconductor device due to the low dielectric constant thereof.
To obtain a higher capacitance in a capacitor formed by applying thereto an NO layer having a limited thickness, a three-dimensional capacitor instead of a planar type capacitor is required. Therefore, layers must be stacked on a substrate or the substrate must be dug down into to form the layers therein. In this way, the effective area for a three-dimensional capacitor can be increased. However, the fabrication process can be complicated, and although a low dielectric constant in an ONO thin film leads to a larger integration, the ONO structure may face limits because of the complicated ONO structure.
In recent years, various approached have been suggested for overcoming the above-described obstacles.
For instance, one approach is focused on a storage node fabrication method using so-called HSG (Hemisphere Grain)--Si for increasing the effective capacitor area in a capacitor which is limited under design rules, structural aspects and so forth. This approach changes a CVD (chemical vapor deposition) silicon surface used as a storage node into a rugged morphology instead of into a smooth one.
Another approach is directed to forming a capacitor dielectric thin film having a high dielectric constant such as Ta.sub.2 O.sub.5 (.di-elect cons..sub.r =2.4) or BST(Ba.sub.x Sr.sub.1-x TiO.sub.3) (.di-elect cons..sub.r =300). However, such technology is difficult to apply in practice because of the sudden decrease of dielectric constant and increased leakage current.
A material Ta.sub.2 O.sub.5 and gaseous O.sub.2 serving as a source of Ta, Ta(OC.sub.2 H.sub.5).sub.5 (penta-ethoxy-tantalum) are employed to form a thin film by simultaneous injection so as to produce an oxide film using a technique such as LPCVD (low-pressure chemical vapor deposition), RF-PECVD or ECR-PECVD.
The dielectric constant of Ta.sub.2 O.sub.5 (.di-elect cons..sub.r =22.about.28) is six times higher than that of SiO.sub.2 and because its leakage current remains low (10.sup.-9 -10.sup.-7 A/cm.sup.-2 under an electric field of 4MV/cm.sup.2) after an appropriate annealing process, Ta.sub.2 O.sub.5 can be applied to a large scale integrated memory device capacitor. Yet, when Si is used as a storage node, oxidation of the silicon surface may be inevitable, resulting in the formation of SiO.sub.2 film thereon. That is, the annealing process after silicon deposition enables the SiO.sub.2 film to grow thicker.
Also, the intermediate SiO.sub.2 film leads to lowering the effective dielectric constant of the dielectric thin film, thereby rendering it difficult to easily obtain a desired capacitance.
It is recommended that the surface of a silicon layer serving as a storage node is nitrided prior to the deposition of Ta.sub.2 O.sub.5 and a silicon nitride film is formed thereon and also Ta.sub.2 O.sub.5 thin film is deposited thereon. In this case, the properties such as dielectric constant, leakage current or TDDB (Time dependent dielectric breakdown) are reported to be superior to those occurring during non-nitridation. Besides, even when a Ta.sub.2 O.sub.5 thin film is applied to a dielectric film, the surface of the silicon electrode maintains a rugged morphology to enable an improvement in capacitance of up to 60%. At this time, because the capacitance remains about 12.5 fF/.mu.m.sup.-2, the Ta.sub.2 O.sub.5 thin film can be put to a practical use, assuming that oxide growth does not occur.
However, when a silicon layer is used as a lower electrode in a capacitor, irrespective of the surface shapes, the high capacitance which is unique to Ta.sub.2 O.sub.5 may not be obtained due to an oxide or nitride film being formed by oxidation or nitridation.